Modern-day semiconductor devices, commonly called microchips or integrated circuits, are fabricated in nearly particle-free “cleanroom” or “wafer fab” environments using a multi-step process that constructs numerous integrated circuits in the form of chips, or “die,” on disc-shaped wafers. Due to the miniscule scale of circuitry on each integrated circuit, it is critical to the fabrication process that the wafers remain as clean and particle-free as possible, as even tiny particles may lead to defects that render a device inoperable, consequently lowering yield and associated profits. Raising the number of good die per wafer is critical to improving fabrication throughput, or the total functional product produced during a certain time period.
With the advent of more advanced technologies, the semiconductor industry is moving in the direction of larger-diameter wafers and smaller die. Consequently, more integrated circuits can be “squeezed” onto a single wafer, contributing to higher throughput. If the defect total for a given wafer area were assumed constant, a smaller die would then encompass fewer defects. However, as smaller circuitry is used within a die, and as the sheer amount of circuitry within each die is concurrently increased, a small defect can be more problematic, as it can contact greater active areas on the die.
In addition, with advancing technology, the number of metal layers within a die is increasing. Polishing and subsequent particle-removal operations are generally associated with each metal layer, so the repetitions of cleaning operations will increase with the number of layers. As defects not removed from one layer can cause problems on subsequent layers, the importance of effectively removing particulate matter from a wafer is increasing. Therefore, more effective and efficient methods are sought for reducing particulate contamination of the wafers during the fabrication process.
Since the late 1950s, integrated circuit technology has evolved rapidly and has revolutionized virtually every industry and capacity in which integrated circuits are used. Today's integrated circuits frequently employ hundreds of thousands or even millions of transistors and highly complex, multi-layered designs. The proliferation of electronics in general, and integrated circuits in particular, has resulted in large part from the ability to increase circuit functionality while simultaneously reducing device cost and size. An important catalyst for these improvements has been advances in semiconductor processing technologies, the various techniques used to construct circuit elements—e.g., transistors, resistors and capacitors—on the semiconductor substrate, as well as the necessary conducting interconnects between individual circuit elements. Improved materials, equipment and processes have allowed increasingly complex circuits with improved speed, reduced power requirements and smaller footprints.
Integrated circuits are typically constructed at the surface of a silicon wafer sliced from a single-crystal ingot, although other semiconductors such as gallium arsenide and germanium are also used. Individual circuit elements are fabricated on the wafer surface. The electrical conduction between appropriate circuit elements, and electrical isolation between other circuit elements, is then established using alternating layers of appropriately patterned conductors and insulators. The circuit elements and their interconnections are formed using a series of processing steps including ion implantation, thin film deposition, photolithography, and selective etching, as well as various cleaning processes.
Each new technology generation brings both increased functionality and an increased number of active metal layers on each die. Integrated circuits are fabricated in layers using several complex operations, with many processes repeated as each layer is created. In a simplified account, after diffusion and deposition steps, metal layers are sputtered onto the wafer. These layers are subsequently subjected to chemical mechanical planarization (CMP), for better planarity to reduce light scattering and for the specific height to ensure proper depth of focus in subsequent photolithography operations.
Photolithography involves spinning a light-sensitive photoresist material onto the wafer surface. Next, using precise optical processes, individual integrated circuits are formed by using a stepper or scanner tool to repetitively expose a pattern on a glass mask, or reticle, in a grid-like fashion onto the photoresist material. If the wafer surface to be exposed is not precisely at the correct distance from the stepper or scanner lens, the exposed image may be out of focus, improperly sized, or otherwise distorted. Such defects can lead to critical dimension losses, as the feature dimensions of an ideally flat wafer are associated with a relatively large geometric tolerance compared to those of a tilted wafer. As die sizes continue to shrink, device features and their associated tolerances will be concurrently smaller, thereby raising the importance of wafer flatness.
After exposure, the exposed photoresist material is normally cured, then developed, typically dissolving exposed areas of the photoresist and leaving the wafer ready for etching or implant doping. The aforementioned processes are generally repeated as each metal layer is fabricated, with some advanced microprocessors requiring seven or more metal layers. Improper exposure due to nonplanarity may also contribute to “hotspots,” defective wafer areas which may include missing or malformed vias, the electrical channels which pass through insulating dielectric layers and connect active metal on one layer to metal on an adjacent layer. Reducing hotspots and other wafer defects contributes to increased tool availability, yield improvements and cost reductions.
As the number of layers fabricated on a wafer increase, planarity and cleanliness of the wafer surface become more important, as minute features created on the wafer surface must line up with corresponding features on the layer below. Such features are often only a fraction of a micron wide (where a micron is one millionth of a meter) so it is critical that the wafer surface be substantially free of topological defects, as with every subsequent layer, any topological defect becomes magnified. Surface non-planarity or particulate matter on the wafer surface can lead to feature registration issues, when the components on adjacent layers do not “line up” properly, potentially leading to nonfunctional or faulty integrated circuits.
A primary challenge in wafer fabrication is the continuing reduction of defect levels. Defects or particles potentially present on wafer surfaces include CMP slurry residue, oxides, organic contaminants, mobile ions and metallic impurities. Generally, a “killer defect” (particle) is less than half the size of the device linewidth. For instance, a device using 0.18-micron (μm) linewidth geometry will require that the wafer be substantially free of particles smaller than 0.09 μm, and at 0.13 μm geometry, particles smaller than 0.065 μm. Due to their smaller size, it is physically more difficult to remove smaller particles than larger particles, so it is beneficial to prevent deposition of particles onto the wafers as much as possible and to develop more effective, comprehensive wafer cleaning methods.
Increasingly complex integrated circuits utilize an growing number of circuit elements, which in turn requires both more electrical conduction paths between circuit elements and a greater number of conductor-insulator layers to achieve these paths. This has proved problematic for several reasons. First, longer interconnect paths means increasing resistance and capacitance, which not only decreases circuit speed by increasing RC-delay times but also increases resistive power loss. Second, an increasing number of layers makes successive layer-to-layer alignment, or registration, more difficult. Layers that lack global and local planarity further compound the registration problem. Historically, the techniques available to improve layer planarity in the semiconductor industry have been quite limited.
Until recently, aluminum was the interconnect conductor of choice in integrated circuit fabrication. Techniques for depositing thin aluminum films are well established and, because aluminum trichloride is somewhat volatile, aluminum can be etched effectively in chlorine plasmas to form patterned aluminum films following appropriate photolithography steps. At the same time, aluminum interconnects have several undesirable properties. First, aluminum is not a particularly good conductor; its resistivity is considerably higher than some other metals. Second, aluminum is particularly susceptible to electromigration, the physical movement of a conductor due to electron flow. Electromigration at grain boundaries results in conductor discontinuities and reduced circuit reliability.
The semiconductor industry is transitioning from aluminum to copper as the electrical conductor of choice for establishing interconnections between circuit elements. Copper has a significantly higher conductivity than aluminum and is inherently more resistant to electromigration. Although these properties of copper have been known for a long time, the absence of acceptable methods for selectively etching or otherwise removing copper have limited its use. Unlike aluminum, copper is not amenable to plasma etch. Thus, a key limitation in moving to copper metallization is the ability to etch or otherwise remove copper at the wafer surface. Improved CMP technologies are facilitating the shift to copper metallization, as CMP not only provides a method for copper removal and for forming patterned copper films, but also addresses the increased need for local and global planarity in complex integrated circuit architectures.
Today, CMP is an essential step in the manufacture of almost every modern integrated circuit. A typical logic device may include upwards of seven inner-layer dielectric (ILD) CMP steps, seven metal CMP steps and one shallow trench isolation (STI) CMP step. Put simply, CMP is quickly becoming a central aspect of semiconductor processing in the formation of integrated circuits.
The CMP operation generally serves to remove excess coating material, reduce wafer topographical imperfections, and improve the depth of focus for photolithography processes through better planarity. The CMP process involves the controlled removal of material on the wafer surface through the combined chemical and mechanical action on the semiconductor wafer of a slurry of abrasive particles and a preferably polyurethane polishing pad embedded with abrasive material. During the CMP operation, sub-micron-size particles from an associated polishing slurry are used to remove non-planar topographical features and extra coating on the wafer surface. After the CMP operation, these ultra-small slurry particles, typically silica (SiO2) or alumina (Al2O3) and residual particles from the polishing pad, as well as metals from the polished wafer may remain on the wafer surface and can be problematic.
The slurries used in CMP are best classified by the types of films they are intended to planarize. In semiconductor manufacturing, CMP processes are most commonly used for films comprised of silicon oxide, tungsten, copper, tantalum and titanium. CMP of copper films, for example, often employs slurries based on ammonia, which offers high copper ion solubility through ion complexation.
In addition to polishing of metallization layers, CMP processing generally also involves barrier layer and dielectric layer polishing. A barrier layer is a layer disposed between two layers that prevent one layer from contaminating the other layer and vice versa. The dielectric layer is frequently comprised of an oxide material such as silica that forms the electrically insulating layer between conducting metal layers. Copper metallization schemes often employ barrier metals such as tantalum or tantalum-rich alloys between the copper and dielectric layers to minimize cross-contamination between those layers. A integrated CMP processing technique should allow the polishing and planarization of alternating layers such as those described—e.g., a layer comprising copper on a layer comprising tantalum on a layer comprising oxide.
Following the CMP process, wafers are typically subjected to a post-CMP cleaning process to remove particulate and molecular contaminants before continuing the construction of the integrated circuit. For wafers processed in batches, rather than individually, storage techniques are used following the CMP process and prior to the post-CMP cleaning process. Storing the wafers frequently consists of placing them in a cassette filled with an appropriate liquid such as water.
For a variety of reasons, currently available post-CMP wafer backside clean techniques are less than optimal. First, the CMP process involves the use of small, abrasive particles that can prove difficult to remove from the wafer surface. Although the slurry particles serve a valuable role during CMP, they constitute particulate defects following the CMP process. Consequently, techniques for improving the removal efficiency of slurry particles are desirable. In addition, molecular contaminants can be introduced during the CMP process that are not always effectively removed during post-CMP cleaning.
As the CMP process is now widely used to provide global planarity of layers during wafer fabrication, successful yield management of CMP requires detection of critical defects such as non-uniform film thickness or process variations within a wafer lot. Defect levels on semiconductor wafers are closely monitored after several operations in the wafer fabrication process. One effective and quick way of measuring defect levels is to subject a wafer to a surface scanning process, which detects surface irregularities and particulate contamination with beams of laser light. CMP defects can generally be separated into two categories: residual slurry particles, metals or other foreign material on the wafer surface, and scratches, grooves or pits in the wafer surface itself. Both defect types are known to have a negative impact on device yield. As is it often difficult to remove minute particles from the surfaces of wafers, new methods for reducing particulate contamination are always being sought. Not only can particles cause killer defects by their very presence, they may also contribute to wafer surface damage, such as the aforementioned scratches, during subsequent post-CMP cleaning operations.
After metal- or dielectric-layer CMP, particle counts on wafer backsides are typically very high. Previously, no process has been dedicated strictly for removal of wafer backside particles. Particles present on wafer backsides are primarily composed of CMP slurry, ranging from smaller than 0.1 micron to 1.0 micron and larger, although with the advent of copper interconnect technology, copper metal residue is also becoming problematic. When particulate matter is present on a wafer backside during photolithography, the wafer may be slightly inclined from horizontal. It then becomes extremely difficult to achieve the precise surface flatness and parallelism required for proper depth of focus for pattern exposure.
Slurry residue on a wafer backside can cause problems beyond an individual wafer. In wafer fabrication, process equipment entities, or tools, are generally cleaned on a regular basis to ensure a virtually particle-free processing environment. During processing, wafers may be removed from a process chamber by a robot arm, which would typically pick up a subsequent wafer and place it into the chamber. If slurry, metal particles or other residue is present on a wafer backside, particulate matter can be spread from one wafer to the next by a robot arm. In this case, the robot arm could potentially contaminate several subsequently handled wafers. Additionally, if several subsequent wafers are also initially contaminated, particulate matter could accumulate on the robot arm, leading to contamination buildup.
In several processing tools, wafers are placed on “chucks,” generally flat surfaces that could collect particulate matter from a contaminated wafer and spread particles to the backside of a subsequent wafer. Contaminated wafers then moving to a subsequent process tool could spread particles to a sequence of tools, contributing to processing defects in a number of fabrication operations. High-pressure deionized (DI) water sprays can also cause migration of particles from a contaminated wafer backside and redeposition onto the wafer front. Additionally, wafers placed adjacent to one another in baths or other holding items such as cassettes may cross-contaminate one another. Preventing contamination caused by the inadvertent deposition of copper on wafer backsides poses a more daunting challenge. This problem has been addressed in part by more stringent requirements imposed on processing equipment and more demanding protocols imposed on manufacturing practices.
Copper contamination is especially troublesome in a fabrication environment, as copper particles can migrate to electrical components on the wafer front, contributing to shorts, leaks and other electrical failures. Copper contamination can arise from tools and equipment involved in the deposition and handling of wafers. For example, a deposition tool that coats wafers with copper films may deposit copper on the beveled edge of the wafer. This wafer may then be sent to a metrology tool equipped with a wafer handler that manipulates the edges of wafers processed in various areas of the fab. This wafer handler, contaminated with copper, may then cross-contaminate wafers that are destined for an etch tool. The etcher eventually becomes contaminated with copper, and the copper contamination spreads through the fab, potentially accumulating in plasma process chambers, wet benches, and lithography steppers.
Wafer handling is the most likely source of copper cross-contamination, since it is the most universal mechanism in a fab. This includes not only automation equipment, such as robots, but also plastic wafer carriers, or cassettes. If copper is left on the wafer bevel as it exits a process tool, the carrier will likely be contaminated with copper. Great care must be taken either to limit the use of wafer carriers to a specified area or to switch to clean carriers once the copper is removed from the bevel. The management of this task can be logistically complex, because most semiconductor equipment is designed for cassette-to-cassette automation —that is, one carrier handles both incoming and outgoing wafers. Cross-contamination, or the spread of particulate matter between wafers and tools or adjacent wafers, is a fabrication issue that can be at least partly addressed by developing improved wafer cleaning methods.
Several prior art methods for post-CMP cleaning exist, two of most common being brush scrubbing and megasonic-assist cleaning. Brush scrubbing is a mechanical contact, single-wafer cleaning process, wherein wafers are passed in succession through a cleaning chamber, where they are contacted with rotating brushes that deliver DI water and cleaning chemicals to the wafer. As conventional brush scrubbing typically only addresses the front side of a wafer, this method is not sufficient to clean particles from wafer backsides. Megasonic-assist cleaning is a wafer cleaning process that can be used in combination with brush scrubbing or other cleaning methods. During megasonic cleaning, a megasonic transducer delivers sonic energy to a wafer through a cleaning medium, generally DI water or a cleaning liquid.
Megasonic-assist cleaning generally loosens particles on a wafer surface being rinsed by DI water or a cleaning medium. The energized wafer surface loosens particles and prevents reattachment of particles. Typically, after the initial rinse, the wafer is subjected to a high-pressure water spray to remove any loosened particles. The wafer may then be passed under and scrubbed by a rotating foam brush to loosen remaining particles, then subjected to another rinse to remove remaining particles.
Currently, after undergoing CMP, wafers are typically subjected to either a single-wafer clean process or a batch clean process. In a typical single-wafer cleaning process, a single wafer may be spun while different cleaning solutions are applied to the wafer surface to be cleaned. In a conventional batch clean process, a batch of wafers is immersed into a plurality of tanks containing various cleaning solutions. Common cleaning methods generally address either metal contamination, or non-metal contamination. In addition, conventional post-CMP cleans are often focused on the wafer front, with little or no attention to specifically removing particulate matter from wafer backsides.
After performing a baseline, or standard, CMP operation, wafers subjected to a conventional batch-clean process wherein wafers are showed higher-than-acceptable defect levels on their backsides during surface-scanning defect detection. When subjected to a conventional post-CMP single-wafer clean process involving dispensing a cleaning medium onto a spinning wafer, wafer backsides showed about a fifty-percent reduction in particles, however, defect levels were still higher than desired. These conventional wafer-cleaning methods suffer from two shortcomings. First, conventional post-CMP cleaning processes are not specifically intended for cleaning the wafer backsides. Second, they are relatively ineffective in removing metal contamination, as conventional cleans are primarily designed to remove non-metallic slurry residue.
Special care is taken in a wafer fabrication environment to prevent the spread of metal particles from one process tool to another. Current methods for removing copper contaminants from wafers utilize nitric (HNO3) acid, which at least partially dissolves copper particles, depending on their size. However, nitric acid is an oxidizing acid that will not remove slurry particles, which consist primarily of silica or alumina, metals that have already oxidized.
Wafer backside defects can account for a significant percentage of yield loss in a wafer fab, causing millions of dollars in lost revenue annually. Backside defects can have a significant impact on wafer and process uniformity, both of which are critical issues in advanced 300-mm wafer processing. The backsides of production wafers may become contaminated or damaged at nearly every process step, including deposition, etch, and chemical mechanical planarization (CMP). The move to double-sided polish wafers for advanced 300-mm semiconductor applications is also creating a challenge, since defects previously hidden in the wafer topography on the backside surface of single-sided polish wafers are brought to the surface when the backside is polished. These defects distort the front surface of wafers during subsequent photolithography exposure, causing yield-destroying “hotspots” of out-of-focus photolithography patterns. Backside defects can also migrate between processes, creating gate dielectric and other failures.
The shortcomings of conventional post-CMP cleaning methods become apparent during post-CMP defect detection, as defect levels are generally higher than desired. It is desired to implement a method for wafer cleaning that simultaneously and effectively removes both metal and non-metal particles from wafer backsides.